? semiconductor components industries, llc, 2007 july, 2007 - rev. 3 1 publication order number: ntmfs4837n/d ntmfs4837n power mosfet 30 v, 74 a, single n-channel, so-8 fl features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? these are pb-free devices applications ? cpu power delivery ? dc-dc converters ? low side switching maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain-to-source voltage v dss 30 v gate-to-source voltage v gs 20 v continuous drain current r ja (note 1) steady state t a = 25 c i d 16 a t a = 85 c 11.5 power dissipation r ja (note 1) t a = 25 c p d 2.2 w continuous drain current r ja (note 2) t a = 25 c id 10 a t a = 85 c 7 power dissipation r ja (note 2) t a = 25 c p d 0.88 w continuous drain current r jc (note 1) t c = 25 c i d 74 a t c = 85 c 53 power dissipation r jc (note 1) t c = 25 c p d 47.2 w pulsed drain current t p =10 s t a = 25 c i dm 148 a operating junction and storage temperature t j , t stg -55 to +150 c source current (body diode) i s 39 a drain to source dv/dt dv/dt 6 v/ns single pulse drain-to-source avalanche energy (v dd = 30 v, v gs = 10 v, i l = 22 a pk , l = 1.0 mh, r g = 25 eas 242 mj lead temperature for soldering purposes (1/8 from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. so-8 flat lead case 488aa style 1 marking diagram http://onsemi.com a = assembly location y = year ww = work week = pb-free package 4837n ayww 1 v (br)dss r ds(on) max i d max 30 v 5.0 m @ 10 v 74 a 7.5 m @ 4.5 v g (4) s (1,2,3) n-channel mosfet d (5,6) device package shipping ? ordering information NTMFS4837NT1G so-8 fl (pb-free) 1500 / tape & reel ntmfs4837nt3g so-8 fl (pb-free) 5000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specifications brochure, brd8011/d. s s s g d d d d (note: microdot may be in either location)
ntmfs4837n http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction-to-case (drain) r jc 2.65 c/w junction-to-ambient C steady state (note 1) r ja 56.75 junction-to-ambient C steady state (note 2) r ja 142.2 1. surface-mounted on fr4 board using 1 sq-in pad, 1 oz cu. 2. surface-mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain-to-source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain-to-source breakdown voltage temperature coefficient v (br)dss / t j 25 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1 a t j = 125 c 10 gate-to-source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 2.5 v negative threshold temperature coefficient v gs(th) /t j 5.7 mv/ c drain-to-source on resistance r ds(on) v gs = 10 v to 11.5 v i d = 30 a 3.5 5.0 m i d = 15 a 3.5 v gs = 4.5 v i d = 30 a 5.9 7.5 i d = 15 a 5.9 forward transconductance g fs v ds = 15 v, i d = 15 a 15 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1 mhz, v ds = 12 v 2048 pf output capacitance c oss 444 reverse transfer capacitance c rss 239 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v; i d = 30 a 14.2 22 nc threshold gate charge q g(th) 2.98 gate-to-source charge q gs 5.7 gate-to-drain charge q gd 6.7 total gate charge q g(tot) v gs = 11.5 v, v ds = 15 v; i d = 15 a 34.2 nc switching characteristics (note 4) turn-on delay time t d(on) v gs = 4.5 v, v ds = 15 v, i d = 15 a, r g = 3.0 14.2 ns rise time t r 55 turn-off delay time t d(off) 19 fall time t f 10 turn-on delay time t d(on) v gs = 11.5 v, v ds = 15 v, i d = 15 a, r g = 3.0 8.5 ns rise time t r 25.6 turn-off delay time t d(off) 25.2 fall time t f 9.2 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntmfs4837n http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise specified) parameter unit max typ min test condition symbol drain-source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 30 a t j = 25 c 0.85 1.2 v t j = 125 c 0.72 reverse recovery time t rr v gs = 0 v, di s /dt = 100 a/ s, i s = 30 a 24 ns charge time t a 13 discharge time t b 11 reverse recovery charge q rr 14 nc package parasitic values source inductance l s t a = 25 c 0.93 nh drain inductance l d 0.005 gate inductance l g 1.84 gate resistance r g 2.8 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures. figure 1. on-region characteristics figure 2. transfer characteristics figure 3. on-resistance vs. v gs figure 4. on-resistance vs. drain current & gate voltage 1 100 0 3 25 4 90 80 70 60 50 40 30 20 10 0 v ds , drain-to-source voltage (v) v gs , gate-to-source voltage (v) 3.8 v t j = 25 c v gs = 10 v to 4.5 v 3.6 v 3.4 v 3.2 v 4v t j = 125 c t j = -55 c t j = 25 c v ds 10 v 12345678 0 100 90 80 70 60 50 40 30 20 10 i d , drain current (a) 0 0.002 0.004 0.006 0.008 20 40 60 90 v gs = 4.5 v v gs = 11.5 v t j = 25 c i d , drain current (a) 0.01 30 80 10 50 70 0.001 0.003 0.005 0.007 0.009 0.003 0.005 0.006 0.008 0.010 0.012 0.014 0.016 0.004 0.007 0.009 0.011 0.013 0.015 t = 25 c i d = 30 a 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 11 v gs , gate-to-source voltage (v) i d , drain current (a) 11.5 r ds(on) , drain-to-source resistance ( ) r ds(on) , drain-to-source resistance ( )
ntmfs4837n http://onsemi.com 4 figure 5. on-resistance variation with temperature figure 6. drain-to-source leakage current vs. voltage figure 7. capacitance variation figure 8. gate-to-source & drain-to-source voltage vs. total charge figure 9. resistive switching time variation vs. gate resistance figure 10. diode forward voltage vs. current 1 10 100 1 10 100 t, time (ns) t r t d(on) t d(off) t f r g , gate resistance ( ) v dd = 15 v i d = 15 a v gs = 11.5 v 1000 100 1000 10000 100000 510152025 30 i dss , leakage (na) 10 1 0 t j = 125 c t j = 150 c v gs = 0 v t j = 25 c v ds , drain-to-source voltage (v) 0 1000 2000 3000 10 5 0 5 10152025 c, capacitance (pf) c oss c rss t j = 25 c v gs v ds c iss 35 30 25 20 15 10 5 0 12 10 8 6 4 2 0 q t q gd q gs v dd = 15.0 v v gs = 11.5 v i d = 30 a t j = 25 c q g , total gate charge (nc) v gs , gate-to-source voltage (v) 0.50 0.60 0.80 15 30 25 20 10 5 0 v gs = 0 v t j = 25 c v sd , source-to-drain voltage (v) i s , source current (a) v ds , drain-to-source voltage (v) 1.40 0.60 t j , junction temperature ( c) r ds(on) , drain-to-source resistance (normalized) -50 25 0 -25 50 75 125 i d = 30 a v gs = 10 v & 4.5 v 100 1.00 150 0.80 1.60 1.80 1.20
ntmfs4837n http://onsemi.com 5 figure 11. maximum rated forward-biased safe operating range figure 12. maximum avalanche energy vs, starting junction temperature figure 13. eas vs. pulse width 25 50 75 100 125 150 t j , starting junction temperature ( c) eas, single pulse drain-to- source av alanche energy (mj) 75 250 225 200 175 150 125 100 50 25 0 i d = 22 a v ds , drain-to-source voltage (v) i d , drain current (a) 100 1000 10 1 100 10 1 0.1 r ds(on) limit thermal limit package limit v gs = 20 v single pulse t c = 25 c 10 s 100 s 10 ms dc 100 100 10 1 1000 1 10 i d (a) pulse width ( s) 100 ms 125 c 100 c 25 c
ntmfs4837n http://onsemi.com 6 package dimensions dfn6 5x6, 1.27p (so8 fl) case 488aa-01 issue c style 1: pin 1. source 2. source 3. source 4. gate 5. drain 6. drain m 3.00 3.40 0 --- 3.80 12 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeter. 3. dimension d1 and e1 do not include mold flash protrusions or gate burrs. 1234 5 6 top view side view bottom view d1 e1 d e 2 2 b a 0.20 c 0.20 c 2 x 2 x dim min nom millimeters a 0.90 1.00 a1 0.00 --- b 0.33 0.41 c 0.23 0.28 d 5.15 bsc d1 4.50 4.90 d2 3.50 --- e 6.15 bsc e1 5.50 5.80 e2 3.45 --- e 1.27 bsc g 0.51 0.61 k 0.51 --- l 0.51 0.61 l1 0.05 0.17 a 0.10 c 0.10 c detail a 14 6 l1 e/2 8x d2 g e2 k b a 0.10 b c 0.05 c l detail a a1 e 3 x c 4 x c seating plane 5 max 1.10 0.05 0.51 0.33 5.10 4.22 6.10 4.30 0.71 --- 0.71 0.20 m *for additional information on our pb-free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 1.270 2x 0.750 1.000 0.905 0.475 4.530 1.530 4.560 0.495 3.200 1.330 0.965 2x 2x 3x 4x 4x on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. typical parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including typicals must be validated for each custom er application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. ntmfs4837n/d publication ordering information n. american technical support : 800-282-9855 toll free ?usa/canada europe, middle east and africa technical support: ?phone: 421 33 790 2910 japan customer focus center ?phone: 81-3-5773-3850 literature fulfillment : ?literature distribution center for on semiconductor ?p .o. box 5163, denver, colorado 80217 usa ? phone : 303-675-2175 or 800-344-3860 toll free usa/canada ? fax : 303-675-2176 or 800-344-3867 toll free usa/canada ? email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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